US 11,809,874 B2
Conditional instructions distribution and execution on pipelines having different latencies for mispredictions
Ethan R Schuchman, Saratoga, CA (US); Niket K Choudhary, Santa Clara, CA (US); Kulin N Kothari, Ellicott City, MD (US); Haoyan Jia, Ellicott City, MD (US); Ian D Kountanis, Santa Clara, CA (US); Douglas C Holman, San Jose, CA (US); Wei-Han Lien, Los Gatos, CA (US); and Pruthivi Vuyyuru, Santa Clara, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 1, 2022, as Appl. No. 17/590,722.
Prior Publication US 2023/0244495 A1, Aug. 3, 2023
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01)
CPC G06F 9/3844 (2013.01) [G06F 9/30058 (2013.01); G06F 9/3836 (2013.01); G06F 9/3861 (2013.01); G06F 9/3885 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor, comprising:
a hardware instruction distribution circuit; and
a plurality of execution pipelines including a first execution pipeline and a second execution pipeline that provide different latencies for processing mispredicted conditional instructions,
wherein the hardware instruction distribution circuit is configured to:
receive a first conditional instruction associated with a prediction; and
distribute the first conditional instruction to one of the first execution pipeline and the second execution pipeline according to the prediction of the first conditional instruction for execution; and
wherein the first execution pipeline is configured to:
in response to receiving the first conditional instruction,
execute the first conditional instruction;
determine that the prediction of the first conditional instruction is a misprediction; and
in response to determining that the prediction of the first conditional instruction is a misprediction, cause the first conditional instruction to be executed in the second execution pipeline.