CPC G06F 9/3844 (2013.01) [G06F 9/30058 (2013.01); G06F 9/3836 (2013.01); G06F 9/3861 (2013.01); G06F 9/3885 (2013.01)] | 20 Claims |
1. A processor, comprising:
a hardware instruction distribution circuit; and
a plurality of execution pipelines including a first execution pipeline and a second execution pipeline that provide different latencies for processing mispredicted conditional instructions,
wherein the hardware instruction distribution circuit is configured to:
receive a first conditional instruction associated with a prediction; and
distribute the first conditional instruction to one of the first execution pipeline and the second execution pipeline according to the prediction of the first conditional instruction for execution; and
wherein the first execution pipeline is configured to:
in response to receiving the first conditional instruction,
execute the first conditional instruction;
determine that the prediction of the first conditional instruction is a misprediction; and
in response to determining that the prediction of the first conditional instruction is a misprediction, cause the first conditional instruction to be executed in the second execution pipeline.
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