US 11,809,873 B2
Selective use of branch prediction hints
Jared W. Stark, Portland, OR (US); Ahmad Yasin, Haifa (IL); and Ajay Amarsingh Singh, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 26, 2020, as Appl. No. 17/033,749.
Claims priority of provisional application 63/017,583, filed on Apr. 29, 2020.
Prior Publication US 2021/0342157 A1, Nov. 4, 2021
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 12/0804 (2016.01)
CPC G06F 9/3842 (2013.01) [G06F 9/30145 (2013.01); G06F 9/3867 (2013.01); G06F 12/0804 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an instruction decoder to decode a branch instruction having a hint; and
a branch predictor to provide a prediction and a hint-override indicator, wherein the hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction, and wherein the prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.