US 11,809,869 B2
Systems and methods to store a tile register pair to memory
Raanan Sade, Kibutz Sarid (IL); Simon Rubanovich, Haifa (IL); Amit Gradstein, Binyamina (IL); Zeev Sperber, Zichron Yackov (IL); Alexander Heinecke, San Jose, CA (US); Robert Valentine, Kiryat Tivon (IL); Mark J. Charney, Lexington, MA (US); Bret Toll, Hillsboro, OR (US); Jesus Corbal, King City, OR (US); Elmoustapha Ould-Ahmed-Vall, Chander, AZ (US); and Menachem Adelman, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 29, 2017, as Appl. No. 15/858,937.
Prior Publication US 2019/0042255 A1, Feb. 7, 2019
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30145 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30043 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A processor comprising:
decode circuitry configured to decode a single store matrix pair instruction specifying an opcode, a first source matrix identifier, and a destination identifier; and
the execution circuitry configured to execute the decoded store matrix pair instruction as per the opcode to:
determine that a pair of matrices are to be stored to memory based on a value, the pair of matrices including a first two-dimensional source matrix and a second two-dimensional source matrix; and
store elements from element positions of the first two-dimensional source matrix to corresponding element positions of a first two-dimensional destination matrix in the memory, and store elements from element positions of the second two-dimensional source matrix to corresponding element positions of a second two-dimensional destination matrix in the memory, in response to the determination that the pair of matrices are to be stored to the memory based on the value.