CPC G06F 3/0656 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0673 (2013.01)] | 21 Claims |
1. A device, comprising:
a plurality of signal processing circuits, which, in operation, perform parallel processing of input sensor data signals and produce output data signals as a function of current and past values of said sensor data signals;
a random access memory (RAM), which, in operation, stores values of the sensor data signals, the RAM having a set of RAM sections; and
RAM management circuitry having a buffer accessible by the plurality of signal processing circuits, and control circuitry, wherein the control circuitry, in operation, manages storage and retrieval of data in sections of the RAM, the managing comprising executing sets of memory operations, a set of memory operations including:
a read operation during which past values of sensor data signals are read from a section of the RAM and stored in the buffer; and
a write operation during which current values of sensor data signals are written into the section of the RAM read during the read operation, overwriting the past values of sensor data signals stored in the section of the RAM.
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