US 11,809,740 B1
Fast and flexible RAM reader and writer
Walter Girardi, Appiano Gentile (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on May 18, 2022, as Appl. No. 17/663,847.
Int. Cl. G11C 29/04 (2006.01); G11C 29/14 (2006.01); G11C 29/56 (2006.01); G06F 13/00 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 29/00 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0671 (2013.01); G11C 7/1036 (2013.01); G11C 29/00 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A circuit for reading or writing a random access memory (RAM), the circuit comprising:
a shift register coupled to the RAM, a test data input, and a test data output; and
a control circuit configured to generate a pulse every N clock cycles, each pulse triggering a RAM access operation transferring data between the shift register and the RAM, N being equal to a data width of the RAM divided by a parallel factor, the parallel factor being a number of pins in either the test data input or the test data output configured for parallel data loading.