US 11,809,724 B2
Memory controller and operating method thereof
Dong Kyu Lee, Icheon-si (KR); Seung Geol Baek, Icheon-si (KR); Jae Hyun Yoo, Icheon-si (KR); and Seon Ju Lee, Icheon-si (KR)
Assigned to SK HYNIX INC., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 7, 2022, as Appl. No. 17/688,689.
Claims priority of application No. 10-2021-0169587 (KR), filed on Nov. 30, 2021.
Prior Publication US 2023/0168827 A1, Jun. 1, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0631 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
13. An operating method of a memory controller that controls a memory device including a plurality of memory blocks allocated to a plurality of zones, the operating method comprising:
generating a plurality of open count values in response to receiving, from an external device, a write request requesting to perform a write operation on a first zone, the open count value for each core indicating a number of zones controlled by a corresponding core and having an open state indicating a capability to execute a program operation; and
determining a second core to perform a write operation corresponding to the write request based on a first open count value corresponding to a first core that controls the first zone.