US 11,809,711 B2
Flash memory scheme capable of decreasing waiting time of trim command
Wen-Chi Hong, Taichung (TW); and Huang-Jhih Ciou, Taipei (TW)
Assigned to Silicon Motion, Inc., Hsinchu County (TW)
Filed by Silicon Motion, Inc., Hsinchu County (TW)
Filed on Jan. 18, 2022, as Appl. No. 17/578,380.
Prior Publication US 2023/0229312 A1, Jul. 20, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 2212/7205 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A flash memory controller used to be externally coupled to a host device and a flash memory, comprising:
a first Input/Output (I/O) interface circuit, coupled between the host device and a bus of the flash memory controller;
the bus;
a second I/O interface circuit, coupled to the bus and the flash memory; and
a multi-processor, having a plurality of processing units each being coupled to the bus, configured to:
receiving a trim command and a logical block address (LBA) range sent from the host device and transferred through the first I/O interface circuit and the bus;
separating multiple operations of the trim command into N threads according to at least one of a number of the processing units, types of the multiple operations, numbers of execution cycles of the multiple operations, and portions of the LBA range, N being an integer equal to or greater than two;
using the processing units to execute the N threads individually; and
increasing a number of execution cycles during which the processing units are busy;
wherein the N threads comprise at least one of following threads: a first thread of checking a state of the LBA range recorded in a logical-to-physical table stored in the flash memory, a second thread of allocating a direct memory access (DMA) first-in-first-out (FIFO) buffer, a third thread of allocating the flash memory's FIFO buffer, a fourth thread of performing a DMA service which is used for loading data of the LBA range and corresponding VPC data from the flash memory into the DMA FIFO buffer, a fifth thread of performing a memory service which is used for loading the data of the LBA range and the corresponding VPC data from the flash memory into the flash memory's FIFO buffer, and a sixth thread of executing a trim operation to erase the data of LBA range and update the corresponding VPC data by decrementing the corresponding VPC data by one sequentially.