US 11,809,360 B2
Network-on-chip data processing method and device
Shaoli Liu, Pudong New Area (CN); Zhen Li, Pudong New Area (CN); and Yao Zhang, Pudong New Area (CN)
Assigned to SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD., Pudong New Area (CN)
Filed by Shanghai Cambricon Information Technology Co., Ltd., Pudong New Area (CN)
Filed on Dec. 29, 2021, as Appl. No. 17/564,411.
Application 17/564,411 is a continuation of application No. 17/278,812, previously published as PCT/CN2019/111977, filed on Oct. 18, 2019.
Claims priority of application No. 201811215820 (CN), filed on Oct. 18, 2018; application No. 201811215978 (CN), filed on Oct. 18, 2018; application No. 201811216718 (CN), filed on Oct. 18, 2018; application No. 201811216857 (CN), filed on Oct. 18, 2018; application No. 201811390409 (CN), filed on Nov. 21, 2018; application No. 201811390428 (CN), filed on Nov. 21, 2018; application No. 201811392232 (CN), filed on Nov. 21, 2018; application No. 201811392262 (CN), filed on Nov. 21, 2018; application No. 201811392270 (CN), filed on Nov. 21, 2018; application No. 201811392279 (CN), filed on Nov. 21, 2018; and application No. 201811393352 (CN), filed on Nov. 21, 2018.
Prior Publication US 2022/0121598 A1, Apr. 21, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/40 (2006.01); G06N 3/04 (2023.01)
CPC G06F 13/4068 (2013.01) [G06N 3/04 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A data processing device, comprising a machine learning device, a transmission circuit, and a shared memory, wherein the machine learning device is connected to the transmission circuit through a first transmission interface, and the transmission circuit is connected to the shared memory;
the transmission circuit is configured to obtain input data required by the machine learning device from the shared memory according to a data operation signal sent by the machine learning device, and return the input data to the machine learning device, where the data operation signal represents an operation mode for data in the shared memory;
wherein the transmission circuit includes: a second transmission interface, at least one read/write processing circuit connected to the second transmission interface, and an arbitration circuit connected to the read/write processing circuit the at least one machine learning unit is connected to the transmission circuit through a connection between the first transmission interface and the second transmission interface;
the read/write processing circuit is configured to receive the data operation signal sent by the at least one machine learning unit through the first transmission interface and the second transmission interface, transmit the data operation signal to the arbitration circuit, and transfer the data read from the shared memory to the at least one machine learning unit through the second transmission interface; and
the arbitration circuit is configured to arbitrate the data operation signal received from the at least one read/write processing circuit according to a preset arbitration rule, and operate the data in the shared memory according to the data operation signal that has been successfully arbitrated.