CPC G06F 13/22 (2013.01) [G06F 1/3225 (2013.01); G06F 13/404 (2013.01); G06F 13/4282 (2013.01); G06F 13/4291 (2013.01); G06F 2213/0016 (2013.01)] | 20 Claims |
1. A device, comprising:
a clock input coupled to a clock line of a bus;
a data input coupled to a data line of the bus;
a clock output coupled to a second device;
a data output coupled to the second device;
an asynchronous address detector that includes a first input coupled to the clock input of the device and a second input coupled to the data input of the device, wherein the asynchronous address detector is configured to monitor the bus for a predefined address that is associated with the second device;
an address regenerator that includes a first output coupled to the clock output of the device and a second output coupled to the data output of the device, wherein the address regenerator is configured to output the predefined address via the second output and a regenerated clock signal via the first output to the second device in response to the second device awaking from a low power sleep mode; and
a controller coupled to the asynchronous address detector and the address regenerator, the controller configured to wake the second device in response to the asynchronous address detector detecting the predefined address.
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