| CPC G06F 13/1668 (2013.01) [G06F 3/061 (2013.01); G06F 3/065 (2013.01); G06F 3/0673 (2013.01)] | 18 Claims |
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1. A memory controller configured to control a memory accessed by a device connected to a host processor via a bus, wherein the device comprises an accelerator circuit, the memory controller comprising:
a first interface circuit configured to communicate with the device;
a second interface circuit configured to communicate with the memory;
a write circuit configured to store first data in the memory based on indirect addressing; and
a read circuit configured to:
identify that a first address included in a first read request received via the first interface circuit from the accelerator circuit is an indirect address of the first data, based on first information included in the first read request,
read a second address from a first region of the memory via the second interface circuit, the first region corresponding to the first address,
in response to the first read request, provide the second address to the accelerator circuit of the device via the first interface circuit, and
prefetch the first data from a second region of the memory via the second interface circuit, the second region corresponding to the second address,
wherein the read circuit is further configured to perform the prefetch by providing a second read command to the memory, together with the second address, without an additional read request issued with respect to the first read request by the accelerator circuit.
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