US 11,809,339 B2
Data bus, data processing method thereof, and data processing apparatus
Keongho Lee, Seoul (KR); Youngseh Kim, Hwaseong-si (KR); Wonjin Kim, Suwon-si (KR); and Seungbeom Lee, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 3, 2021, as Appl. No. 17/191,255.
Claims priority of application No. 10-2020-0028654 (KR), filed on Mar. 6, 2020.
Prior Publication US 2021/0279190 A1, Sep. 9, 2021
Int. Cl. G06F 13/16 (2006.01); G06F 16/23 (2019.01)
CPC G06F 13/1668 (2013.01) [G06F 16/2379 (2019.01)] 19 Claims
OG exemplary drawing
 
1. A data bus comprising:
a transaction selection circuit configured to receive vector data including a plurality of transactions from outside of the data bus, select at least one transaction from the plurality of transactions in which no traffic conflict occurs based on whether there is a traffic conflict among the plurality of transactions with reference to a conflict table, and output the selected at least one transaction; and
a memory data path comprising at least one register and configured to output the selected at least one transaction provided by the transaction selection circuit via the at least one register to the outside of the data bus,
wherein the transaction selection circuit selects a row of the conflict table associated with a first transaction of the transactions, references element values of columns of the selected row to determine at least one second transaction of the transactions that has no conflict with the first transaction and sets the at least one transaction to at least one of the first transaction and the at least one second transaction and performs a logical OR operation on at least one column in the conflict table by using all element values included in the corresponding column.