US 11,809,338 B2
Shared memory for intelligent network interface cards
Francesc Guim Bernat, Barcelona (ES); Daniel Rivas Barragan, Cologne (DE); Kshitij A. Doshi, Tempe, AZ (US); and Mark A. Schmisseur, Phoenix, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 4, 2021, as Appl. No. 17/492,928.
Application 17/492,928 is a continuation of application No. 15/475,216, filed on Mar. 31, 2017, granted, now 11,157,422.
Prior Publication US 2022/0204542 A1, Jun. 30, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 13/16 (2006.01); G06F 12/0817 (2016.01); H04L 12/46 (2006.01); C07F 15/00 (2006.01); G06F 12/0831 (2016.01); G06F 12/1018 (2016.01); H04L 49/90 (2022.01)
CPC G06F 13/1663 (2013.01) [C07F 15/0033 (2013.01); G06F 12/082 (2013.01); G06F 12/0822 (2013.01); G06F 12/0831 (2013.01); G06F 12/1018 (2013.01); H04L 12/4625 (2013.01); H04L 49/9068 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/621 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A network interface, comprising:
a hardware bus interface circuit to communicatively couple the network interface to a host computer, wherein the host computer has a central processor unit (CPU);
a memory circuit comprising a shareable memory region that can be cache coherently mapped to an address space of the host computer;
a coprocessor circuit to provide an accelerated network support function via the shareable memory region; and
a caching agent (CA) circuit to maintain cache coherency between the coprocessor and the CPU via the shareable memory region.