US 11,809,334 B2
Integrated circuit with asymmetric access privileges
Neil Whyte, Edinburgh (GB); Michael Chandler-Page, Stonehouse (GB); Pradeep Saminathan, Edinburgh (GB); and Jon Eklund, Austin, TX (US)
Assigned to Cirrus Logic Inc., Austin, TX (US)
Filed by Cirrus Logic International Semiconductor Ltd., Edinburgh (GB)
Filed on Apr. 16, 2021, as Appl. No. 17/232,514.
Claims priority of provisional application 63/138,950, filed on Jan. 19, 2021.
Prior Publication US 2022/0229784 A1, Jul. 21, 2022
Int. Cl. G06F 12/14 (2006.01); G06F 3/16 (2006.01); G06F 9/4401 (2018.01); G06F 21/60 (2013.01); G06F 21/62 (2013.01); G06F 21/74 (2013.01); G06F 21/85 (2013.01); G06F 21/76 (2013.01); G06F 13/16 (2006.01)
CPC G06F 12/1441 (2013.01) [G06F 13/1668 (2013.01); G06F 2212/1052 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit configured to drive an audio transducer, the integrated circuit comprising:
first and second interfaces; and
an internal addressable space comprising a plurality of address ranges;
wherein the integrated circuit stores an access permission to define an authorized subset of address ranges to which access by an external processor is permitted during runtime control of the integrated circuit;
wherein each of the first and second interfaces is coupled to the internal addressable space, and wherein each of the first and second interfaces is configured to receive a request, from the external processor, to access at least one of the address ranges of the internal addressable space; and
wherein the integrated circuit is configurable in a first state in which the external processor is permitted, via the first interface, access to the authorized subset of address ranges and is prevented, via the first interface, access to the remainder of the address ranges during runtime control of the integrated circuit and the external processor is permitted, via the second interface, access to the plurality of address ranges, and configurable in a second state in which the external processor is permitted, via the second interface, access to the authorized subset of address ranges and is prevented, via the second interface, access to the remainder of the address ranges during runtime control of the integrated circuit and the external processor is permitted, via the first interface, access to the plurality of address ranges.