US 11,809,321 B2
Memory management in a multiple processor system
Wael Noureddine, Santa Clara, CA (US); Jean-Marc Frailong, Rancho Mirage, CA (US); Pradeep Sindhu, Los Altos Hills, CA (US); and Bertrand Serlet, Palo Alto, CA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Jun. 10, 2022, as Appl. No. 17/806,419.
Application 17/806,419 is a continuation of application No. 16/791,957, filed on Feb. 14, 2020, granted, now 11,360,895.
Application 16/791,957 is a continuation of application No. 15/949,892, filed on Apr. 10, 2018, granted, now 10,565,112, issued on Feb. 18, 2020.
Claims priority of provisional application 62/483,844, filed on Apr. 10, 2017.
Claims priority of provisional application 62/625,518, filed on Feb. 2, 2018.
Prior Publication US 2022/0300423 A1, Sep. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0815 (2016.01); G06F 12/0804 (2016.01); G06F 15/173 (2006.01)
CPC G06F 12/0815 (2013.01) [G06F 12/0804 (2013.01); G06F 15/17325 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1032 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computing system comprising a first processing unit, a second processing unit, and shared memory, and wherein the computing system is configured to:
enable the first processing unit to modify data in the shared memory, including:
accessing the data in the shared memory,
storing the data in a cache associated with the first processing unit,
modifying the data in the cache to yield updated data, and
flushing the cache to store the updated data in the shared memory;
receive an indication that modifying data in the shared memory is complete;
after receiving the indication that modifying the shared memory is complete, deliver a message to the second processing unit, wherein the message specifies operations that access the shared memory; and
enable, after delivering the message, the second processing unit to execute the operations that access the shared memory.