US 11,809,319 B2
Contention tracking for processor cache management
Anurag Chaudhary, San Jose, CA (US); Christopher Richard Feilbach, Santa Clara, CA (US); Jasjit Singh, San Francisco, CA (US); Manuel Gautho, Truckee, CA (US); Aprajith Thirumalai, Santa Clara, CA (US); and Shailender Chaudhry, Santa Clara, CA (US)
Assigned to Nvidia Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Jan. 20, 2022, as Appl. No. 17/580,353.
Prior Publication US 2023/0244603 A1, Aug. 3, 2023
Int. Cl. G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/123 (2016.01)
CPC G06F 12/0811 (2013.01) [G06F 12/0815 (2013.01); G06F 12/123 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A system comprising:
a cache that comprises a shared cache and a private cache; and
a processing device, operatively coupled with the cache, to perform operations comprising:
identifying a first location and a second location in a memory, wherein the first location comprises first data and the second location comprises second data;
determining whether the first location is contentious and whether the second location is contentious;
responsive to the first location being contentious, storing the first data in the shared cache, wherein the shared cache is used by a plurality of processing cores;
responsive to the second location being uncontentious, bypassing the shared cache and storing the second data in the private cache, wherein the private cache is used by a processing core of the plurality of processing cores;
storing contention data associated with the first location in a data structure of the processing device responsive to the first location being contentious at a first time; and
updating the contention data responsive to the first location no longer being contentious at a second time.