CPC G06F 12/0615 (2013.01) [G06F 12/0284 (2013.01); G06F 12/0646 (2013.01); G06F 13/124 (2013.01); G06F 2213/0026 (2013.01)] | 14 Claims |
1. A data operation method for an artificial intelligence chip, wherein the artificial intelligence chip comprises a chip memory, a base address register, an extended address processor, and a computing processor, wherein the data operation method comprises:
allocating an extended address space for accessing the chip memory to the base address register, wherein the extended address space is greater than a physical memory address space of the chip memory;
receiving, by the extended address processor, a command carrying first data and address information;
determining, by the extended address processor, an operation mode of the first data according to the address information pointing to one among a plurality of sections comprised in the extended address space;
performing, by the extended address processor, a first operation on the first data when the address information points to a first section of the extended address space; and
notifying, by the extended address processor, the computing processor of the operation mode, performing, by the computing processor, a second operation on the first data when the address information points to a section other than the first section of the extended address space,
wherein the first section corresponds to the physical memory address space.
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