US 11,809,220 B1
Adaptive memory error detection and correction
Deepak Kumar Agarwal, Bangalore (IN); Kunal Desai, Bangalore (IN); Jimit Shah, Bangalore (IN); and Rakesh Gehalot, Bangalore (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM INCORPORATED, San Diego, CA (US)
Filed on Apr. 20, 2022, as Appl. No. 17/725,170.
Int. Cl. G06F 11/10 (2006.01)
CPC G06F 11/1044 (2013.01) 34 Claims
OG exemplary drawing
 
1. A method for adaptive memory error detection and correction (EDAC), comprising:
monitoring EDAC logic of a memory subsystem for error corrections with the EDAC logic configured to use a first EDAC level;
determining a number of error corrections using the first EDAC level during a first time interval;
determining whether the number of error corrections using the first EDAC level during the first time interval exceeds a first threshold; and
switching the EDAC logic from using the first EDAC level to using a second EDAC level when the number of error corrections using the first EDAC level during the first time interval exceeds the first threshold.