US 11,809,206 B2
Methods and apparatus to implement compensation circuitry in an envelope detector
Kishalay Datta, Kolkata (IN); Anant Shankar Kamath, Bangalore (IN); Kumar Anurag Shrivastava, Bangalore (IN); and Swaminathan Sankaran, Allen, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Aug. 26, 2021, as Appl. No. 17/446,132.
Prior Publication US 2023/0069663 A1, Mar. 2, 2023
Int. Cl. G05F 1/46 (2006.01); G05F 1/56 (2006.01); H03F 1/02 (2006.01); H04B 1/16 (2006.01)
CPC G05F 1/56 (2013.01) [H03F 1/0216 (2013.01); H04B 1/16 (2013.01); H03F 2200/102 (2013.01); H03F 2200/165 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a compensation circuit including:
a current compensation output;
a first transistor with a first current terminal and a first control terminal, the first current terminal coupled to the current compensation output; and
a resistor ladder with a tap terminal coupled to the first control terminal;
a current mirror circuit having a mirror input and a mirror output, the mirror input coupled to the current compensation output; and
a rectification circuit having an input coupled to the mirror output.