US 11,808,975 B2
Semiconductor structure and fabrication method thereof
Jun Liu, Shanghai (CN); Hong Gang Dai, Shanghai (CN); and Dong Xiang Cheng, Shanghai (CN)
Assigned to Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed by Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed on Dec. 27, 2021, as Appl. No. 17/646,125.
Claims priority of application No. 202011587896.X (CN), filed on Dec. 28, 2020.
Prior Publication US 2022/0206217 A1, Jun. 30, 2022
Int. Cl. G02B 6/12 (2006.01); G02B 6/10 (2006.01); G02B 6/122 (2006.01); G02B 6/136 (2006.01)
CPC G02B 6/122 (2013.01) [G02B 6/136 (2013.01); G02B 2006/12061 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a base substrate;
an optical waveguide layer over the base substrate;
a first dielectric layer over the base substrate, wherein a cavity is formed between the first dielectric layer and the optical waveguide layer, and the cavity is located on sidewall surfaces of the optical waveguide layer and has a bottom coplanar with a bottom of the optical waveguide layer, and the cavity is filled with air; and
a second dielectric layer on the first dielectric layer and the optical waveguide layer, wherein the second dielectric layer is located on a top of the cavity and seals the cavity.