CPC G01R 31/40 (2013.01) [G01R 19/0092 (2013.01)] | 24 Claims |
1. A system, comprising:
a first connection from a first node to a second node, the first connection including a first transistor and a first diode in parallel with the first transistor, wherein the first transistor is configured to allow current flow between the first node and the second node through the first transistor when the first transistor is enabled, and the first diode is configured to allow current flow between the first node and the second node when the first transistor is disabled;
a second connection from the first node to the second node, the second connection including a second transistor and a second diode in parallel with the second transistor, wherein the second transistor is configured to allow current flow between the first node and the second node through the second transistor when the second transistor is enabled, and the second diode is configured to allow current flow between the first node and the second node when the second transistor is disabled; and
a fault detection circuit configured to test the first connection by detection of current flow along the second connection while the second transistor is disabled, and configured to test the second connection by detection of current flow along the first connection while the first transistor is disabled.
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