| US 7,617,377 B2 | ||
| Splitting endpoint address translation cache management responsibilities between a device driver and device driver services | ||
| Daniel F. Moertl, Rochester, Minn. (US); Renato J. Recio, Austin, Tex. (US); Claudia A. Salzberg, Austin, Tex. (US); and Steven M. Thurber, Austin, Tex. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Oct. 17, 2006, as Appl. No. 11/550,115. | ||
| Prior Publication US 2008/0092148 A1, Apr. 17, 2008 | ||
| Int. Cl. G06F 12/10 (2006.01) | ||
| U.S. Cl. 711—206 [711/118; 711/202] | 5 Claims |
| 1. A method, in a data processing system, for managing address translations for accessing a memory of the data processing
system, comprising:
invoking, by a device driver, device driver services for initializing address translation entries in an address translation
data structure of a root complex of the data processing system;
creating, by the device driver services, one or more address translation data structure entries in the address translation
data structure associated with the root complex by:
passing, by the device driver, to device driver services one or more addresses in a first address space that references addresses
used by the device driver and operating system;
translating, by the device driver services, one or more addresses in the first address space into one or more addresses in
the second address space, where the second address space references translated addresses used by the root complex to reference
real memory;
storing, by the device driver services, in the address translation data structure of a root complex of the data processing
system one or more translation entries from a third address space that references untranslated I/O bus addresses, which are
translated into one or more addresses in the second address space by the root complex before they are used to reference real
memory; and
passing, by the device driver services, to the device driver one or more addresses in the third address space;
caching at least one of the one or more address translation data structure entries in a cache of an input/output (I/O) device
coupled to the data processing system; and
bypassing the address translation data structure associated with the root complex for a received I/O operation associated
with an address for which an address translation data structure entry is present in the cache of the I/O device;
determining if a direct memory access (DMA) transaction from the I/O device is directed to an address in the third address
space for which there is a cached address translation data structure entry in the cache of the I/O device; and
modifying the I/O operation request to include an address in the second address space corresponding to the address in the
third address space and to set a “translated” identifier in the DMA transaction to indicate that the DMA transaction contains
a translated address, if the DMA transaction is directed to an address in the third address space for which there is a cached
address translation data structure entry in the cache of the I/O endpoint.
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