an interface for monitoring signals asserted by said processor device when performing processor cache updates, said signals including update indicator signals for each cache update occurring, an update indicator signal for each cache update being associated with a particular cache line in a set i, where i ∈{1, . . . , N} within said N-way set-associative cache; and,

for each set i, a cache wrap detection logic means responsive to said update indicator signals for detecting a wrap condition in said set i, and, asserting a set_wrap(i) signal when all lines within that set have been replaced,

a means for receiving each said asserted set_wrap(i) signal and generating a cache wrap detection signal when a cache wrap has occurred for all sets of said N-way set associative cache and all lines of the cache memory device have been replaced relative to said identified starting state,

wherein said monitored signals further comprise a cache way signal indicating a current cache line being replaced in a particular set i, said cache wrap detection logic means comprising:

a register device loaded with data indicating a single cache way that must be updated to complete a set wrap condition in said set i; and,

comparator means for receiving said cache way signals and asserting a signal when a received cache way signal matches the loaded cache way data content of the register device.