| US 7,617,346 B2 | ||
| Rapid input/output doorbell coalescing to minimize CPU utilization and reduce system interrupt latency | ||
| Chi-Lie Wang, Milpitas, Calif. (US); Kwong Hou Mak, Millbrae, Calif. (US); and Jason Z. Mo, Fremont, Calif. (US) | ||
| Assigned to Integrated Device Technology, Inc., San Jose, Calif. (US) | ||
| Filed on Feb. 27, 2007, as Appl. No. 11/679,823. | ||
| Prior Publication US 2008/0209139 A1, Aug. 28, 2008 | ||
| Int. Cl. G06F 13/26 (2006.01) | ||
| U.S. Cl. 710—264 | 30 Claims |
| 1. A doorbell system comprising a system device that includes:
a plurality of flag registers, each having a corresponding flag register address, and each having a plurality of flag entries
for storing status/error information associated with the system device;
a flag scan controller configured to monitor the flag registers, and activate a doorbell request upon detecting that one or
more of the flag entries of a flag register is asserted; and
a doorbell generator configured to receive the activated doorbell request, and in response, route the flag entries and the
flag register address of the flag register as a doorbell command.
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