| US 7,616,507 B2 | ||
| Microprocessor boot-up controller, nonvolatile memory controller, and information processing system | ||
| Hiroshi Sukegawa, Tokyo (Japan); Kenji Sakaue, Kanagawa (Japan); and Hitoshi Tsunoda, Kanagawa (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Aug. 14, 2007, as Appl. No. 11/838,463. | ||
| Application 11/838463 is a division of application No. 11/084039, filed on Mar. 21, 2005, granted, now 7,464,259. | ||
| Claims priority of application No. 2004-086737 (JP), filed on Mar. 24, 2004. | ||
| Prior Publication US 2007/0291540 A1, Dec. 20, 2007 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—189.11 [365/185.17; 365/185.18; 365/185.24; 365/235] | 9 Claims |
| 1. A memory system including a nonvolatile semiconductor memory device and a controller, the memory device comprising:
a plurality of word lines; and
a plurality of memory cells, each connected to a corresponding one of the word lines and each having N threshold voltages
for storing multi-valued level, where N is a natural number of 4 or greater,
wherein stored data in each of the plurality of memory cells constitutes a plurality of pages, at least only a part of multi-value
level is used for storing data, a data “1” is always written to a lower page, a “0” or “1” binary data is written to an upper
page, the same data is written in each of the pages when writing in the nonvolatile memory device, and only part of the pages
to which the same data is written is accessed when reading out the nonvolatile memory device.
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