| US 7,616,021 B2 | ||
| Method and device for determining an operational lifetime of an integrated circuit device | ||
| Vassilios Papageorgiou, Austin, Tex. (US); Amado Ramirez, Austin, Tex. (US); and Michael Zhouying Su, Round Rock, Tex. (US) | ||
| Assigned to Advanced Micro Devices, Inc., Sunnyvale, Calif. (US) | ||
| Filed on Jan. 18, 2007, as Appl. No. 11/624,258. | ||
| Prior Publication US 2008/0174329 A1, Jul. 24, 2008 | ||
| Int. Cl. G01R 31/26 (2006.01) | ||
| U.S. Cl. 324—765 | 3 Claims |
| 1. A method comprising:
determining a power mode of an operation of an activated integrated circuit device;
applying a test electrical bias to a degradable test structure of the integrated circuit device via an external interface
pin of the integrated circuit device, wherein a magnitude of the test electrical bias is based on the power mode for the operation
of the integrated circuit;
determining a degradable characteristic of the degradable test structure in response to the application of the test electrical
bias to the degradable test structure; and
determining an estimated cumulative duration for which the integrated circuit device has been in operation based on the degradable
characteristic.
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