| US 7,615,818 B2 | ||
| Semiconductor device and method of manufacturing the same | ||
| Eiji Sakagami, Kanagawa (Japan); and Makoto Nakashima, Kanagawa (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Oct. 03, 2006, as Appl. No. 11/538,272. | ||
| Claims priority of application No. 2005-291231 (JP), filed on Oct. 04, 2005. | ||
| Prior Publication US 2007/0097777 A1, May 03, 2007 | ||
| Int. Cl. H01L 29/76 (2006.01) | ||
| U.S. Cl. 257—314 [257/288; 257/315; 438/264; 438/296] | 1 Claim |
| 1. A semiconductor device comprising:
a semiconductor substrate;
a plurality of floating gate electrodes formed in a memory cell forming region on the semiconductor substrate;
a word line having a first width electrically connecting the floating gate electrodes; and
a plurality of ellipse conductor portions having a second width narrower than the first width formed on the word line to reduce
a resistance of the word line,
wherein a center of the ellipse conductor portion is positioned at a mid portion between drain contacts of transistors forming
the word lines and memory cells, and wherein a major axis of the ellipse conductor portion is arranged no greater than twice
a cell pitch in the word line direction.
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