| US 7,615,808 B2 | ||
| Structure for implementation of back-illuminated CMOS or CCD imagers | ||
| Bedabrata Pain, Los Angeles, Calif. (US); and Thomas J. Cunningham, Pasadena, Calif. (US) | ||
| Assigned to California Institute of Technology, Pasadena, Calif. (US) | ||
| Filed on Sep. 13, 2005, as Appl. No. 11/226,903. | ||
| Claims priority of provisional application 60/610830, filed on Sep. 17, 2004. | ||
| Claims priority of provisional application 60/610831, filed on Sep. 17, 2004. | ||
| Prior Publication US 2006/0076590 A1, Apr. 13, 2006 | ||
| Int. Cl. H01L 27/146 (2006.01); H01L 31/09 (2006.01) | ||
| U.S. Cl. 257—228 [257/233; 257/292; 257/294; 257/444; 257/447; 257/460; 257/E27.133] | 28 Claims |
| 1. A backside illuminated imaging structure comprising:
a passivation layer;
a silicon layer connected with the passivation layer, acting as a junction anode, the silicon layer adapted to convert light
passing through the passivation layer and collected by the imaging structure to photoelectrons;
a semiconductor well of a first conductivity type, located opposite the passivation layer with respect to the silicon layer,
acting as a junction cathode;
a transistor connected to the imaging structure, wherein a doped region of the transistor is located within the silicon layer;
and
a reflector layer adapted to receive photons passing through the silicon layer and to reflect the photons back to the silicon
layer.
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