| US 7,615,436 B2 | ||
| Two mask floating gate EEPROM and method of making | ||
| Igor G. Kouznetsov, Santa Clara, Calif. (US); and Andrew J. Walker, Mountain View, Calif. (US) | ||
| Assigned to SanDisk 3D LLC, Milpitas, Calif. (US) | ||
| Filed on May 20, 2004, as Appl. No. 10/849,152. | ||
| Application 10/849152 is a division of application No. 10/066376, filed on Feb. 05, 2002, granted, now 6,897,514. | ||
| Application 10/066376 is a continuation in part of application No. 09/927648, filed on Aug. 13, 2001, granted, now 6,881,994. | ||
| Claims priority of provisional application 60/279855, filed on Mar. 28, 2001. | ||
| Prior Publication US 2004/0207001 A1, Oct. 21, 2004 | ||
| Int. Cl. H01L 21/8238 (2006.01) | ||
| U.S. Cl. 438—201 [438/211; 438/257; 257/E27.078; 257/E21.179] | 42 Claims |
| 1. A method of making a floating gate transistor, comprising:
providing a semiconductor active area;
forming a tunnel dielectric layer over the active area;
forming a floating gate layer over the tunnel dielectric layer;
forming a first photoresist mask over the floating gate layer;
patterning the floating gate layer using the first photoresist mask to form a floating gate rail;
doping the active area using the floating gate rail as a mask to form source and drain regions in the active area;
forming an intergate insulating layer adjacent to lower portions of side surfaces of the floating gate rail;
forming a control gate dielectric layer over and adjacent to upper portions of the side surfaces of the floating gate rail;
forming a control gate layer over the control gate dielectric layer;
forming a second photoresist mask over the control gate layer; and
patterning the control gate layer, the control gate dielectric layer, the floating gate rail, the tunnel dielectric layer
and the active area using the second photoresist mask to form a control gate, a control gate dielectric, a floating gate,
a tunnel dielectric and a channel island region.
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