| US 7,615,426 B2 | ||
| PMOS transistor with discontinuous CESL and method of fabrication | ||
| Chih-Hao Wang, Hsin-Chu (Taiwan); Yen-Ping Wang, Taipei (Taiwan); and Pang-Yen Tsai, Jhu-bei (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (Taiwan) | ||
| Filed on Apr. 29, 2005, as Appl. No. 11/118,730. | ||
| Claims priority of provisional application 60/655142, filed on Feb. 22, 2005. | ||
| Prior Publication US 2006/0189053 A1, Aug. 24, 2006 | ||
| Int. Cl. H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 27/01 (2006.01) | ||
| U.S. Cl. 438—197 [257/347; 257/344; 257/336] | 19 Claims |
| 1. A transistor comprising:
a substrate having a surface;
a gate dielectric on said surface of said substrate;
a gate electrode on said gate dielectric;
a spacer along a sidewall of said gate dielectric and gate electrode;
a source and a drain formed on opposite sides, respectively, of said gate dielectric and said gate electrode, the source and
drain defining a channel region having a channel length extending substantially from said source to said drain, in the substrate
therebetween;
a contact etch stop layer on said gate electrode and said spacers, and said source and drain, wherein said contact etch stop
layer comprises a discontinuity extending in a channel width direction;
an inter-level dielectric over said contact etch stop layer;
a first contact opening over said gate electrode;
a second contact opening over one of said source and said drain, wherein said discontinuity is between said first and second
contact openings, and wherein the discontinuity does not adjoin the first and the second contact openings.
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