| US 7,615,162 B2 | ||
| Printed wiring board and method for manufacturing the same | ||
| Motoo Asai, Gifu (Japan); Yasuji Hiramatsu, Gifu (Japan); Yoshinori Wakihara, Gifu (Japan); and Kazuhito Yamada, Gifu (Japan) | ||
| Assigned to IBIDEN Co., Ltd., Ibi-Gun (Japan) | ||
| Filed on Sep. 19, 2006, as Appl. No. 11/522,960. | ||
| Application 10/351501 is a division of application No. 09/319258, granted, now 6,835,895, previously published as PCT/JP97/04684, filed on Dec. 18, 1997. | ||
| Application 11/522960 is a continuation of application No. 11/203427, filed on Aug. 15, 2005. | ||
| Application 11/203427 is a continuation of application No. 10/351501, filed on Jan. 27, 2003, granted, now 6,930,255. | ||
| Claims priority of application No. 8-354971 (JP), filed on Dec. 19, 1996; application No. 8-357959 (JP), filed on Dec. 27, 1996; application No. 8-357801 (JP), filed on Dec. 28, 1996; application No. 9-29587 (JP), filed on Jan. 28, 1997; application No. 9-197526 (JP), filed on Jul. 23, 1997; and application No. 9-197527 (JP), filed on Jul. 23, 1997. | ||
| Prior Publication US 2007/0051694 A1, Mar. 08, 2007 | ||
| Int. Cl. H01B 13/00 (2006.01) | ||
| U.S. Cl. 216—13 [216/17; 216/19; 29/592.1] | 9 Claims |
| 1. A method of producing a multilayer printed circuit board comprising:
providing a structure having a substrate, at least one first conductor circuit formed on the substrate and having a surface
at least partially roughened, and an insulating layer formed on the substrate and the at least one first conductor circuit;
forming at least one opening for a viahole structure connecting to the at least one first conductor circuit through the insulating
layer;
subjecting the insulating layer with the opening to an electroless plating to form an electroless plated film having a thickness
of 0.1-5 μm;
forming a plating resist on the electroless plated film;
subjecting the electroless plated film and the plating resist over the insulating layer to an electrolytic plating so as to
form an electrolytic plated film having a thickness of 5-30 μm;
removing the plating resist; and
etching and removing the electroless plated film exposed by a pattern of the plating resist by applying an etching solution
to form at least one second conductor circuit comprising the electroless plated film and the electrolytic plated film, and
the viahole structure electrically connected between the first conductor circuit and the second conductor circuit.
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