| US 7,447,091 B2 | ||
| Sense amplifier for semiconductor memory device | ||
| Tomonori Sekiguchi, Tama (Japan); Shinichi Miyatake, Ome (Japan); Takeshi Sakata, Hino (Japan); Riichiro Takemura, Tokyo (Japan); Hiromasa Noda, Tokyo (Japan); and Kazuhiko Kajigaya, Iruma (Japan) | ||
| Assigned to Hitachi, Ltd., Tokyo (Japan); Elpida Memory, Inc., Tokyo (Japan); and Hitachi ULSI Systems Co., Ltd., Tokyo (Japan) | ||
| Filed on Feb. 15, 2007, as Appl. No. 11/706,409. | ||
| Application 11/706409 is a continuation of application No. 10/534049, granted, now 7,200,061, filed on Apr. 03, 2007, previously published as PCT/JP02/11659, filed on Nov. 08, 2002. | ||
| Prior Publication US 2007/0147152 A1, Jun. 28, 2007 | ||
| Int. Cl. G11C 7/02 (2006.01) | ||
| U.S. Cl. 365—207 [365/205] | 2 Claims |
| 1. A semiconductor memory device comprising:
a first amplifier circuit having first and second N-channel MOS transistors and first and second P-channel MOS transistors;
and
a second amplifier circuit for amplifying, to a power-supply voltage amplitude, information read from a memory cell,
wherein a gate of said first N-channel MOS transistor and a gate of said second N-channel MOS transistor are connected to
a first power-supply potential, a source of said first N-channel MOS transistor is connected to a first input terminal, and
a source of said second N-channel MOS transistor is connected to a second input terminal,
a gate of said first P-channel MOS transistor and a gate of said second P-channel MOS transistor are connected to a ground
potential, a source of said first P-channel MOS transistor and a source of said second P-channel MOS transistor are connected
to said first power-supply potential,
a drain of said first N-channel MOS transistor is connected to a drain of said first P-channel MOS transistor, and a drain
of said second N-channel MOS transistor is connected to a drain of said second N-channel MOS transistor, and
said first and second N-channel MOS transistors receive inputs of the information read from said memory cell prior to said
first and second P-channel MOS transistors.
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