| US 7,447,071 B2 | ||
| Low voltage column decoder sharing a memory array p-well | ||
| Massimiliano Frulio, Milan (Italy); Stefano Surico, Milan (Italy); Andrea Sacco, Alessandria (Italy); and Davide Manfre, Pandino (Italy) | ||
| Assigned to Atmel Corporation, San Jose, Calif. (US) | ||
| Filed on Nov. 08, 2006, as Appl. No. 11/557,627. | ||
| Prior Publication US 2008/0123415 A1, May 29, 2008 | ||
| Int. Cl. G11C 11/34 (2006.01) | ||
| U.S. Cl. 365—185.11 [365/230.03; 365/230.06] | 19 Claims |
| 1. A non-volatile memory array having a hierarchical column decoding configuration with two or more levels of column decoding,
comprising:
a substrate having a p-well region;
a plurality of memory sub-arrays that are formed in said p-well region, each of said memory sub-arrays having at least one
first-level column decoder for selecting one of said plurality of column output terminals;
a last-level decoder that is formed outside of said p-well region and that receives column output signals from the first-level
column decoders;
wherein said last-level column decoders are formed as high-voltage MOS device outside of said p-well region;
a first high-voltage switch that is activated during a memory erase mode of operation to provide a high voltage to bias the
p-well region; and
a plurality of high-voltage switches that are activated during a memory erase mode of operation to provide a high voltage
to respective gate terminals of the selector transistors in the first-level column decoders.
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