| US 7,447,038 B2 | ||
| Module | ||
| Yutaka Uematsu, Hachioji (Japan); Hideki Osaka, Oiso (Japan); Yoji Nishio, Sagamihara (Japan); and Seiji Funaba, Hitachinaka (Japan) | ||
| Assigned to Elpida Memory, Inc., Tokyo (Japan) | ||
| Filed on Dec. 16, 2005, as Appl. No. 11/304,625. | ||
| Claims priority of application No. 2004-365004 (JP), filed on Dec. 16, 2004. | ||
| Prior Publication US 2006/0133055 A1, Jun. 22, 2006 | ||
| Int. Cl. H05K 1/00 (2006.01) | ||
| U.S. Cl. 361—748 [361/780; 361/792; 361/793; 361/794; 361/795; 257/691; 257/723; 257/724] | 25 Claims |
| 1. A module comprising
a semiconductor device using a reference voltage and a module base plate mounted with a plurality of the semiconductor devices,
wherein the module base plate is mounted on a system base plate; reference voltage input portions of the plurality of the
semiconductor devices mounted on the module base plate are connected with decoupling capacitors and reference voltage power
source planes constituting a parallel plate with a Vss layer; and
the decoupling capacitors and the reference voltage power source planes are provided near the semiconductor devices such that
one of the decoupling capacitors and one of the reference voltage power source planes are assigned for each of the semiconductor
devices individually.
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