| US 7,446,570 B2 | ||
| Shift register, gate driving circuit and display panel having the same, and method thereof | ||
| Myung-Woo Lee, Suwon-si (Korea, Republic of); Sang-Jin Pak, Yongin-si (Korea, Republic of); Joo-Hyung Lee, Gwacheon-si (Korea, Republic of); Hyung-Guel Kim, Yongin-si (Korea, Republic of); Man-Seung Cho, Seoul (Korea, Republic of); and Kee-Han Uh, Yongin-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Jun. 29, 2007, as Appl. No. 11/771,253. | ||
| Application 11/771253 is a continuation of application No. 11/242387, filed on Oct. 03, 2005, granted, now 7,250,788. | ||
| Claims priority of application No. 10-2004-0078306 (KR), filed on Oct. 01, 2004. | ||
| Prior Publication US 2008/0001627 A1, Jan. 03, 2008 | ||
| Int. Cl. H03K 19/0175 (2006.01) | ||
| U.S. Cl. 326—83 [326/46; 345/99] | 18 Claims |
| 1. A shift register comprising a plurality of stages, each of the stages generating an output signal in sequence, each of
the stages comprising:
a buffering section receiving one of a scan start signal and an output signal of a previous stage;
a driving section generating the output signal of a present stage, when the buffering section receives one of the scan start
signal and the output signal of a previous stage; and
a driving control section applying the output signal of a next stage to the driving section,
wherein the driving control section controls the driving section based on the output signal of the next stage so that the
source voltage is applied to the driving section.
|