| US 7,446,262 B2 | ||
| Laminated electronic component and method for producing the same | ||
| Nobuaki Ogawa, Omihachiman (Japan); Norio Sakai, Moriyama (Japan); and Yoshihiko Nishizawa, Yasu (Japan) | ||
| Assigned to Murata Manufacturing Co., Ltd., Kyoto (Japan) | ||
| Appl. No. 10/549,005 PCT Filed Jan. 06, 2005, PCT No. PCT/US2005/000051 § 371(c)(1), (2), (4) Date Sep. 14, 2005, PCT Pub. No. WO2005/071745, PCT Pub. Date Aug. 04, 2005. |
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| Claims priority of application No. 2004-018285 (JP), filed on Jan. 27, 2004. | ||
| Prior Publication US 2007/0026196 A1, Feb. 01, 2007 | ||
| Int. Cl. H05K 1/03 (2006.01) | ||
| U.S. Cl. 174—255 [174/260; 174/261] | 15 Claims |
| 1. A laminated electronic component comprising:
a combined laminate including:
a ceramic substrate having a first principal surface, a second principal surface, side surfaces, and a recess continuously
extending on a peripheral portion of the first principal surface; and
a resin layer that is compression bonded and heat-cured to the first principal surface of the ceramic substrate; wherein
a portion of a peripheral portion of the resin layer is embedded in the recess;
an outer terminal electrode is provided on an outer surface of the resin layer; and
the recess extends from at least one of the side surfaces into the first principal surface so as to define a stair shape.
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