| US 7,446,007 B2 | ||
| Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof | ||
| James W. Adkisson, Jericho, Vt. (US); Marc W. Cantell, Sheldon, Vt. (US); James R. Elliott, Huntington, Vt. (US); James V. Hart, III, Barre, Vt. (US); and Dale W. Martin, Hyde Park, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Nov. 17, 2006, as Appl. No. 11/560,893. | ||
| Prior Publication US 2008/0116493 A1, May 22, 2008 | ||
| Int. Cl. H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—303 [438/595; 257/E21.626] | 13 Claims |
| 1. A method for fabricating a semiconductor structure comprising:
forming a topographic feature over a substrate;
forming a multilayer spacer adjoining a sidewall of the topographic feature, the multilayer spacer comprising a first spacer
sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that
is other than the deposited silicon oxide material; and
treating the multilayer spacer with a chemical oxide removal (COR) etchant to recess the first spacer sub-layer with respect
to the second spacer sub-layer, where the chemical oxide removal etchant comprises a gaseous mixture of ammonia and hydrogen
fluoride that provides an etch limiting residue within a recess of the first spacer sub-layer with respect to the second spacer
sub-layer.
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