| US 7,445,966 B2 | ||
| Method and structure for charge dissipation during fabrication of integrated circuits and isolation thereof | ||
| John J. Ellis-Monaghan, Grand Isle, Vt. (US); Jeffrey P. Gambino, Westford, Vt. (US); Timothy D. Sullivan, Underhill, Vt. (US); and Steven H. Voldman, South Burlington, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jun. 24, 2005, as Appl. No. 11/160,468. | ||
| Prior Publication US 2007/0013072 A1, Jan. 18, 2007 | ||
| Int. Cl. H01L 23/60 (2006.01) | ||
| U.S. Cl. 438—122 [438/926; 438/666; 438/637; 438/622; 257/712] | 19 Claims |
| 8. A method, comprising:
placing integrated circuit element shapes comprising substrate contact, contact, single-damascene wire, dual-damascene wire
or via shapes in a hierarchal set of design levels from a lowest to a highest design level of an integrated circuit chip;
placing charge dissipation structure shapes comprising additional substrate contact, additional contact, additional wire or
additional via shapes in each design level of said hierarchal set of design levels, within each design level said charge dissipation
structure shapes not contacting said integrated circuit element shapes, said charge dissipation shapes in each design level
electrically connected to one another and not electrically connected to any contact, via or single-damascene wire shape of
said integrated circuit element shapes in immediately lower design levels of said hierarchal set of design levels; and
within one or more of said design levels of said hierarchal set of design levels, placing fill-shapes, said fill shapes not
contacting each other, said integrated circuit element shapes or said charge dissipation structure shapes of a same design
level of said hierarchal set of design levels.
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