| US 7,614,025 B1 | ||
| Method of placement for iterative implementation flows | ||
| Raymond Kong, San Francisco, Calif. (US); and Sandor S. Kalman, Santa Clara, Calif. (US) | ||
| Assigned to XILINX, Inc., San Jose, Calif. (US) | ||
| Filed on Apr. 18, 2007, as Appl. No. 11/787,785. | ||
| Int. Cl. G06F 17/50 (2006.01); G06F 9/45 (2006.01) | ||
| U.S. Cl. 716—10 [716/1; 716/8; 716/9; 716/11; 716/12; 716/13] | 16 Claims |
| 1. A computer-implemented method of implementing a circuit design in a target device, the method comprising:
executing a program by a computer system to perform functions including:
identifying routing information for a circuit design that has been at least partially implemented;
identifying a plurality of empty sites of the target device within which the circuit design is to be implemented;
determining whether each of the plurality of empty sites of the target device has a routing conflict according to the routing
information of the circuit design;
wherein determining whether each of the plurality of empty sites of the target device has a routing conflict further includes
determining whether at least one pin of each of the plurality of empty sites has a blockage;
determining that a pin does not have a blockage when, while traversing a directed acyclic graph representing routing information
with respect to the pin, a node is identified that is not used and has an incoming degree of at least two;
generating a list specifying each of the plurality of empty sites of the target device that has a routing conflict; and
outputting the generated list.
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