| US 7,613,966 B2 | ||
| Hyperjtag system including debug probe, on-chip instrumentation, and protocol | ||
| Ernest Lewis Edgar, Larkspur, Colo. (US); and Bruce J. Ableidinger, Portland, Oreg. (US) | ||
| Assigned to MIPS Technologies, Inc., Mountain View, Calif. (US) | ||
| Filed on Jan. 05, 2009, as Appl. No. 12/348,847. | ||
| Application 12/348847 is a continuation of application No. 11/026324, filed on Dec. 29, 2004, granted, now 7,475,303, filed on Jan. 06, 2009. | ||
| Claims priority of provisional application 60/533331, filed on Dec. 29, 2003. | ||
| Prior Publication US 2009/0119555 A1, May 07, 2009 | ||
| Int. Cl. G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—724 | 5 Claims |
| 1. A port-sharing device, comprising:
multiple processor cores on a chip, at least a sub-set of processor cores being coupled to corresponding off-chip test probes,
wherein communication of signals between a specific processor core of the sub-set of processor cores and a corresponding off-chip
test probe is interleaved in time layers with signals from each of the remaining processor cores in the sub-set of processor
cores, wherein processor cores of the sub-set of processor cores are independently and simultaneously controlled.
|