US 7,613,960 B2
Semiconductor device test apparatus and method
Kazuyoshi Okawa, Tokyo (Japan); Junko Ogino, Tokyo (Japan); Masayuki Yoshinaga, Tokyo (Japan); and Hajime Honda, Tokyo (Japan)
Assigned to Advantest Corporation, Tokyo (Japan)
Appl. No. 10/588,636
PCT Filed Feb. 18, 2004, PCT No. PCT/JP2004/001805
§ 371(c)(1), (2), (4) Date Aug. 04, 2006,
PCT Pub. No. WO2005/078736, PCT Pub. Date Aug. 25, 2005.
Prior Publication US 2007/0265794 A1, Nov. 15, 2007
Int. Cl. G11C 29/00 (2006.01)
U.S. Cl. 714—710  [714/718; 365/200; 365/201] 13 Claims
OG exemplary drawing
 
5. A semiconductor device test method comprising the steps of:
(a) performing a function test on a specific type memory device under test that has a specific redundancy structure and has specific repair conditions to obtain information about defective memory cells;
(b) preparing a general-purpose memory repair analysis program that is designed to perform memory repair analysis for a regular type memory device having no specific redundancy structure and having regular repair conditions other than the specific repair conditions, which comprises individual operations constituting a process of the repair analysis, and which includes user function insertion points between the operations;
(c) preparing a user analysis program which is designed to perform the specific repair conditions of the specific type memory device and comprises user functions that are to be inserted to user function insertion points to make a change to data processed by the memory repair analysis program based on the specific repair analysis conditions; and
(d) performing repair analysis of the defective memory cell information of the specific type memory device in accordance with the general-purpose memory repair analysis program by inserting the user functions to the user function insertion points.