US 7,613,859 B2
Back-off timing mechanism in a digital signal processor
Shigehiro Asano, Yokosuka (Japan); and Tsutomu Ishii, Tokyo (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Sep. 12, 2007, as Appl. No. 11/853,898.
Prior Publication US 2009/0070507 A1, Mar. 12, 2009
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/00 (2006.01)
U.S. Cl. 710—110  [710/310; 713/400] 20 Claims
OG exemplary drawing
 
1. A back-off timing system implemented in a digital signal processor (DSP) comprising:
a command buffer configured to store a plurality of entries;
a running counter configured to count cyclically through a set of values;
one or more comparators configured to, for each entry, compare selected bits of a timer expiration value corresponding to the entry with corresponding bits of the current value of the running counter; and
wherein the DSP is configured to initiate an action corresponding to a first one of the entries in response to the one or more comparators determining that the selected bits of the timer expiration value corresponding to the first one of the entries matches the corresponding bits of the current value of the running counter.