a selection circuit configured for receiving a first prescribed number of phase signals representing respective equally-spaced phases of a clock signal, the selection circuit configured for selecting and outputting, from the first prescribed number of phase signals, first and second adjacent phase signals based on a phase selection value representing one of a second prescribed number of phases, the second prescribed number a multiple of the first prescribed number, the selection circuit further configured for outputting a digital interpolation control value based on the phase selection value relative to the first and second adjacent phase signals;

first and second binary weighted current sources configured for outputting first and second contribution currents onto a summing node based on the first and second adjacent phase signals, respectively, and based on the digital interpolation control value, the first and second contribution currents forming at the summing node an interpolated signal that is interpolated relative to the first and second adjacent phase signals and the digital interpolation control value; and

an amplifier circuit configured for outputting the interpolated signal as a phase-interpolated clock signal, having a voltage swing between a first reference voltage and a second reference voltage, according to the phase selection value.