| US 7,613,067 B2 | ||
| Soft error robust static random access memory cells | ||
| Manoj Sachdev, 55 Leighland Drive, Waterloo, Ontario N2T 2K2 (Canada); and Shah M Jahinuzzaman, 9 Amos Avenue, Apt. 8, Waterloo, Ontario N2L 2W6 (Canada) | ||
| Filed on Oct. 22, 2007, as Appl. No. 11/876,223. | ||
| Claims priority of provisional application 60/853034, filed on Oct. 20, 2006. | ||
| Prior Publication US 2008/0094925 A1, Apr. 24, 2008 | ||
| Int. Cl. G11C 8/00 (2006.01) | ||
| U.S. Cl. 365—230.06 [365/154; 365/200; 365/230.08] | 8 Claims |
| 1. A Static Random Access Memory (SRAM) cell comprising:
first and second storage nodes configured to store complementary voltages;
access transistors configured to selectively couple the first and second storage nodes to a corresponding bit-line;
drive transistors configured to selectively couple one of the first and second storage nodes to ground;
load transistors configured to selectively couple the other one of the first and second storage nodes to a power supply; and
at least one stabilizer transistor configured to provide a corresponding redundant storage node and limit feedback between
the first and second storage nodes, the redundant storage node being capable of restoring the first or second storage nodes
in case of a soft error.
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