| US 7,613,064 B1 | ||
| Power management modes for memory devices | ||
| Barry A. Wagner, San Jose, Calif. (US); Andrew R. Bell, San Francisco, Calif. (US); Thomas E. Dewey, Menlo Park, Calif. (US); and Russell R. Newcomb, Morgan Hill, Calif. (US) | ||
| Assigned to nVidia Corporation, Santa Clara, Calif. (US) | ||
| Filed on Dec. 19, 2006, as Appl. No. 11/612,919. | ||
| Int. Cl. G11C 5/14 (2006.01) | ||
| U.S. Cl. 365—227 [365/222; 365/233] | 19 Claims |
| 1. A memory device, comprising:
one or more memory banks;
timing logic to periodically perform self-refresh of said one or more memory banks;
locking logic to at least partially maintain synchronization between an internal clock of the memory device and an external
clock during performance of first and second modes, wherein said self-refresh is performed during said second mode; and
a locking logic controller to control one or more portions of said locking logic, wherein said locking logic controller is
adapted to reduce an amount of power supplied to the locking logic during said performance of said self-refresh.
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