| US 7,613,062 B2 | ||
| Semiconductor memory device in which data is stored in nonvolatile state, by using semiconductor elements of metal oxide semiconductor (MOS) structure | ||
| Hiroaki Nakano, Yokohama (Japan); Toshimasa Namekawa, Tokyo (Japan); Hiroshi Ito, Yokohama (Japan); Osamu Wada, Yokohama (Japan); and Atsushi Nakayama, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Apr. 23, 2007, as Appl. No. 11/738,774. | ||
| Claims priority of application No. 2006-183712 (JP), filed on Jul. 03, 2006. | ||
| Prior Publication US 2008/0002504 A1, Jan. 03, 2008 | ||
| Int. Cl. G11C 17/18 (2006.01) | ||
| U.S. Cl. 365—225.7 [365/189.19; 365/96] | 12 Claims |
| 1. A semiconductor memory device comprising:
a first data line and a second data line connected to each of a plurality of sense amplifiers; and
a plurality of memory cells arranged in rows and columns, each of the memory cells including a memory element and first and
second selection transistors,
wherein:
the memory element includes a semiconductor element of metal oxide semiconductor (MOS) structure, and data is programmed when
an insulating film is broken down by application of a voltage;
the first selection transistor connects the memory element to the first data line in order to program data;
the second selection transistor connects the memory element to the second data line in order to program data and sense the
programmed data, the second selection transistor having a gate-electrode width that is smaller than that of the first selection
transistor; and
each of the memory cells further includes a first electric-field mitigating transistor connected between the memory element
and the first and second selection transistors, a third selection transistor connected between the first selection transistor
and the first data line, and a second electric-field mitigating transistor connected between the second selection transistor
and the first electric-field mitigating transistor.
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