US 7,613,048 B2
Nonvolatile semiconductor memory device and nonvolatile memory system
Atsushi Inoue, Tokyo (Japan); and Toshifumi Shano, Yokkaichi (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Nov. 02, 2007, as Appl. No. 11/934,330.
Claims priority of application No. 2006-299572 (JP), filed on Nov. 02, 2006.
Prior Publication US 2008/0106946 A1, May 08, 2008
Int. Cl. G11C 16/04 (2006.01)
U.S. Cl. 365—185.24  [365/185.28; 365/185.17; 365/185.09] 20 Claims
OG exemplary drawing
 
1. A nonvolatile semiconductor memory device comprising;
a memory cell array including a plurality of electrically rewritable nonvolatile memory cells arranged in series, at least one of said memory cells storing data using a plurality of threshold levels;
a threshold level storage section storing a programming method switch threshold level on which a first programming method and a second programming method are switched;
a comparison circuit comparing said programming method switch threshold level with a programming data threshold level and outputting a comparison result;
a control signal generation circuit setting said first programming method or said second programming method based on said comparison result and outputting a control signal corresponding to said first programming method or said second programming method; and
a voltage generation circuit generating a programming voltage and an intermediate voltage which are applied to said at least one memory cell based on said control signal.