US 7,613,046 B2
Nonvolatile semiconductor memory device carrying out simultaneous programming of memory cells
Noboru Shibata, Yokohama (Japan); and Tomoharu Tanaka, Yokohama (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Jul. 02, 2007, as Appl. No. 11/772,271.
Application 11/194716 is a division of application No. 10/442995, filed on May 22, 2003, granted, now 6,937,512.
Application 11/772271 is a continuation of application No. 11/530340, filed on Sep. 08, 2006, granted, now 7,295,469.
Application 11/530340 is a continuation of application No. 11/194716, filed on Aug. 02, 2005, granted, now 7,106,627.
Application 10/442995 is a continuation of application No. 09/957019, filed on Sep. 21, 2001, granted, now 6,600,676.
Claims priority of application No. 2000-297443 (JP), filed on Sep. 28, 2000.
Prior Publication US 2007/0280017 A1, Dec. 06, 2007
Int. Cl. G11C 16/34 (2006.01)
U.S. Cl. 365—185.22  [365/185.12; 365/185.11; 365/185.17; 365/185.03; 365/185.04; 365/185.09] 3 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a plurality of memory elements to which data is written by a write operation; and
a control circuit, wherein:
in a first write sequence, the control circuit simultaneously stores data in “n” (“n” being a natural number) numbers of said plurality of the memory elements in the write operation and then the control circuit repeats the write operation and a verify operation if any of said “n” numbers of the memory elements are memory elements written insufficiently in the verify operation; and
in a second write sequence, the control circuit simultaneously stores data in “n” (“n” being a natural number) numbers of said plurality of the memory elements in the write operation and then the control circuit repeats the write operation and a verify operation if “k” (“k” being a natural number which is equal to or less than “n”) or greater numbers of said “n” numbers of the memory elements are memory elements written insufficiently in the verify operation.