| US 7,613,041 B2 | ||
| Methods for operating semiconductor device and semiconductor memory device | ||
| Chih-Hsin Wang, 6585 Gillis Dr., San Jose, Calif. 95120 (US) | ||
| Filed on Sep. 25, 2006, as Appl. No. 11/464,404. | ||
| Application 11/464404 is a division of application No. 11/055427, filed on Feb. 09, 2005, granted, now 7,297,634. | ||
| Application 11/055427 is a continuation in part of application No. 11/007907, filed on Dec. 08, 2004, granted, now 7,115,942. | ||
| Application 11/007907 is a continuation in part of application No. 10/457249, filed on Jun. 06, 2003, granted, now 6,958,513. | ||
| Prior Publication US 2007/0008778 A1, Jan. 11, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 11/34 (2006.01) | ||
| U.S. Cl. 365—185.01 [365/185.19] | 20 Claims |
| 1. A method of operating a semiconductor device having a strained tunneling gate, strained ballistic gate disposed adjacent
to and insulated from the strained tunneling gate, a storage region disposed adjacent to and insulated from the strained ballistic
gate, and a strain source providing a mechanical stress to the strained tunneling gate and the strained ballistic gate to
provide a piezo-effect, the method comprising the steps of:
applying a first voltage to the strained tunneling gate;
applying a second voltage to the strained ballistic gate; and
applying a third voltage to the storage region to inject charge carriers from the strained tunneling gate through the strained
ballistic gate into the storage region.
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