| US 7,613,038 B2 | ||
| Semiconductor integrated circuit device | ||
| Riichiro Takemura, Tokyo (Japan); Takeshi Sakata, Hino (Japan); Norikatsu Takaura, Tokyo (Japan); and Kazuhiko Kajigaya, Iruma (Japan) | ||
| Assigned to Hitachi, Ltd., Tokyo (Japan); and Elpida Memory, Inc., Tokyo (Japan) | ||
| Filed on Jan. 13, 2009, as Appl. No. 12/352,668. | ||
| Application 12/352668 is a continuation of application No. 11/832727, filed on Aug. 02, 2007, granted, now 7,492,644. | ||
| Application 11/832727 is a continuation of application No. 11/598702, filed on Nov. 14, 2006, granted, now 7,257,034. | ||
| Application 11/598702 is a continuation of application No. 10/995198, filed on Nov. 24, 2004, granted, now 7,154,788. | ||
| Claims priority of application No. 2003-398398 (JP), filed on Nov. 28, 2003. | ||
| Prior Publication US 2009/0122602 A1, May 14, 2009 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—163 [365/205] | 4 Claims |
| 1. A semiconductor integrated circuit device comprising:
a memory cell array having a plurality of word lines, a plurality of bit lines across the plurality of word lines, and a plurality
of memory cells provided at intersections of the plurality of word lines and the plurality of bit lines, each of the plurality
of memory cells having a phase-change resistance;
a word driver coupled to the plurality of word lines; and
a column selector having a plurality of sense amplifiers coupled to the plurality of bit lines,
wherein, when the semiconductor integrated circuit device receives a first command with a first address, the word driver selects
one of the plurality of word lines according to the first address, and the plurality of sense amplifiers amplifies first data
read out from the plurality of memory cells by selecting one of the plurality of word lines and holds the first data therein,
wherein, when the semiconductor integrated circuit device receives a second command, which indicates a write operation, with
a second address and second data next to the first command, the column selector selects a part of the plurality of sense amplifiers
according to the second address and inputs the second data to the part of the plurality of sense amplifiers to change a part
of first data to the second data,
wherein, when the semiconductor integrated circuit device receives a third command, which indicates a read operation, with
a third address next to the first command, the column selector selects a part of the plurality of sense amplifiers according
to the third address and outputs a part of first data held in the selected sense amplifiers.
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