| US 7,613,032 B2 | ||
| Semiconductor memory device and control method thereof | ||
| Tomoaki Yabe, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Feb. 07, 2008, as Appl. No. 12/27,548. | ||
| Claims priority of application No. 2007-029398 (JP), filed on Feb. 08, 2007. | ||
| Prior Publication US 2008/0192527 A1, Aug. 14, 2008 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—154 [365/189.16; 365/222] | 20 Claims |
| 1. A semiconductor memory device comprising:
a plurality of memory cells each including a first inverter and a second inverter, a first storage node connected to an output
terminal of the first inverter and an input terminal of the second inverter, and a second storage node connected to an input
terminal of the first inverter and an output terminal of the second inverter;
a word line connected to the memory cells; and
a plurality of bit lines connected to the memory cells, respectively,
wherein input data is written to a selected memory cell, and data read from an non-selected memory cell is written again to
the non-selected memory cell in write operation.
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